1. Field of the Invention
Embodiments of the present invention relate to compositions and methods for removing a conductive material from a substrate.
2. Background of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of interconnects is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
Multilevel interconnects are formed using sequential material deposition and material removal techniques on a substrate surface to form features therein. As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization prior to further processing. Planarization or “polishing” is a process in which material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing excess deposited material, removing undesired surface topography, and surface defects, such as surface roughness, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials to provide an even surface for subsequent photolithography and other semiconductor manufacturing processes. One conventional process for planarization is by chemical mechanical polishing (CMP), which planarizes a layer by chemical activity and mechanical activity,
It is extremely difficult to planarize a metal surface, particularly a copper surface, as of a damascene inlay as shown in FIGS. 1A and 1B, with a high degree of surface planarity using a chemical mechanical polishing process. A damascene inlay formation process may include etching feature definitions in an interlayer dielectric, such as a silicon oxide layer, sometimes including a barrier layer in the feature definition and on a surface of the substrate, and depositing a thick layer of copper material on the substrate surface and any barrier layer if present. Chemical mechanically polishing the copper material to remove excess copper above the substrate surface often insufficiently planarizes the copper surface. Chemical mechanical polishing techniques to completely remove the copper material often results in topographical defects, such as dishing and erosion that may affect subsequent processing of the substrate.
Dishing occurs when a portion of the surface of the inlaid metal of the interconnection formed in the feature definitions in the interlayer dielectric is excessively polished, resulting in one or more concave depressions, which may be referred to as concavities or recesses. Referring to FIG. 1A, a damascene inlay of lines 11 are formed by depositing copper (Cu) or a copper alloy, in a damascene opening formed in interlayer dielectric 10, for example, silicon dioxide. While not shown, a barrier layer of a suitable material such as titanium (or tantalum) and/or titanium nitride (or tantalum nitride) for copper may be deposited between the interlayer dielectric 10 and the inlaid metal 12. Subsequent to planarization, a portion of the inlaid metal 12 may be depressed by an amount D, referred to as the amount of dishing. Dishing is more likely to occur in wider or less dense features on a substrate surface.
Additionally, residual material may remain after a polishing process. In such instances a second polishing step or an overpolishing process may be performed to remove the remaining material. However, such processes may result in erosion, characterized by excessive polishing of the layer not targeted for removal, such as a dielectric layer surrounding a metal feature. Referring to FIG. 1 B, a copper line 21 and dense array of copper lines 22 are inlaid in interlayer dielectric 20. The process to polish the copper lines 22 may result in loss, or erosion E, of the dielectric 20 between the metal lines 22. Erosion is observed to occur near narrower or more dense features formed in the substrate surface. Modifying conventional copper CMP polishing techniques has resulted in less than desirable polishing rates and less than desirable polishing results than commercially acceptable.
Therefore, there is a need for compositions and methods for removing conductive material, such as excess copper material, from a substrate that minimizes the formation of topographical defects to the substrate during planarization.